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MC14526B Presettable 4-Bit Down Counters
The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for divide-by-N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
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MARKING DIAGRAMS
MC14526BCP AWLYYWWG 1 PDIP-16 1 P SUFFIX CASE 648
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * Logic Edge-Clocked Design: Incremented on Positive Transition of * * *
Clock or Negative Transition of Inhibit Asynchronous Preset Enable Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range Pb-Free Packages are Available*
14526B AWLYWWG 1 SOIC-16 WB DW SUFFIX CASE 751G 1
MAXIMUM RATINGS
Rating DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation per Package (Note 1) Operating Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 1 SOEIAJ-16 F SUFFIX CASE 966 1 MC14526B ALYWG
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
1
April, 2006 - Rev. 5
Publication Order Number: MC14526B/D
MC14526B
FUNCTION TABLE
Inputs Clock X X X X L H H Reset H H H L L L L L L L Inhibit X X X X H L L Preset Enable L H X H L L L L L L Cascade Feedback L L H X X X L L L L Output "0" L H H L L L L L L L Resulting Function Asynchronous reset* Asynchronous reset Asynchronous reset Asynchronous preset Decrement inhibited Decrement inhibited No change** (inactive edge) No change** (inactive edge) Decrement** Decrement** Q3 P3 PE INHIBIT P0 CLOCK VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q2 P2 CF 0" P1 RESET Q1
Figure 1. Pin Assignment
X = Don't Care NOTES: ** Output "0" is low when reset goes high only it PE and CF are low. ** Output "0" is high when reset is low, only if CF is high and count is 0000.
PIN DESCRIPTIONS other than all zeroes, the "0" output is valid after the rising Preset Enable (Pin 3) -- If Reset is low, a high level on the edge of Preset Enable (when Cascade Feedback is high). See Preset Enable input asynchronously loads the counter with the Function Table. the programmed values on P0, P1, P2, and P3. Inhibit (Pin 4) -- A high level on the Inhibit input pre- Cascade Feedback (Pin 13) -- If the Cascade Feedback vents the Clock from decrementing the counter. With Clock input is high, a high level is generated at the "0" output when (pin 6) held high, Inhibit may be used as a negative edge clock the count is all zeroes. If Cascade Feedback is low, the "0" input. output depends on the Preset Enable input level. See the Function Table. Clock (Pin 6) -- The counter decrements by one for each rising edge of Clock. See the Function Table for level P0, P1, P2, P3 (Pins 5, 11, 14, 2) -- These are the preset requirements on the other inputs. data inputs. P0 is the LSB. Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) -- These are the Reset (Pin 10) -- A high level on Reset asynchronously forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is synchronous counter outputs. Q0 is the LSB. high, causes the "0" output to go high. VSS (Pin 8) -- The most negative power supply potential. "0" (Pin 12) -- The "0" (Zero) output issues a pulse one This pin is usually ground. clock period wide when the counter reaches terminal count VDD (Pin 16) -- The most positive power supply potential. (Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and VDD may range from 3.0 to 18 V with respect to VSS. Preset Enable is low. When presetting the counter to a value
STATE DIAGRAM MC14526B
0 1 2 3 4
15
5
14
6
13
7
12
11
10
9
8
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MC14526B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD Characteristic Output Voltage Vin = VDD or 0 "0" Level Symbol VOL Vdc -55C Min - - - Max 0.05 0.05 0.05 Min - - - 25C Typ (Note 2) 0 0 0 Max 0.05 0.05 0.05 125C Min - - - Max 0.05 0.05 0.05 Unit Vdc
5.0 10 15
"1" Level Vin = 0 or VDD Output Voltage Vin = VDD or 0 "0" Level VOH 5.0 10 15 4.95 9.95 14.95 - - - 4.95 9.95 14.95 5.0 10 15 - - - 4.95 9.95 14.95 - - - Vdc
"1" Level Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Source IOH 5.0 5.0 10 15 IOL 5.0 10 15 15 - 5.0 10 15 5.0 10 15 -3.0 -0.64 -1.6 -4.2 0.64 1.6 4.2 - - - - - - - - - - - - 0.1 - 5.0 10 20 -2.4 -0.51 -1.3 -3.4 0.51 1.3 3.4 - - - - - -4.2 -0.88 -2.25 -8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 - - - - - - - 0.1 7.5 5.0 10 20 -1.7 -0.36 -0.9 -2.4 0.36 0.9 2.4 - - - - - - - - - - - - 1.0 - 150 300 600 mAdc mAdc "0" Level VIH 5.0 10 15 "1" Level 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - Vdc "0" Level VIL 5.0 10 15 "1" Level - - - 1.5 3.0 4.0 - - - 2.25 4.50 6.75 1.5 3.0 4.0 - - - 1.5 3.0 4.0 Vdc
Sink
Iin Cin
mAdc pF mAdc
IT = (1.7 mA/kHz) f + IDD IT = (3.4 mA/kHz) f + IDD IT = (5.1 mA/kHz) f + IDD
mAdc
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
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MC14526B
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) (Note 5)
Characteristic Symbol VDD 5.0 10 15 Min - - - Typ (Note 6) 100 50 40 Max 200 100 80 Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL (Figures 4, 5) Propagation Delay Time (Inhibit Used as Negative Edge Clock) Clock or Inhibit to Q tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns Clock or Inhibit to "0" tPLH, tPHL = (1.7 ns/pF) CL + 155 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Propagation Delay Time Pn to Q Propagation Delay Time Reset to Q Propagation Delay Time Preset Enable to "0" Clock or Inhibit Pulse Width tPLH, tPHL (Figures 4, 5, 6) 5.0 10 15 5.0 10 15 tPLH, tPHL (Figures 4, 7) tPHL (Figure 8) tPHL, tPLH (Figures 4, 9) tw (Figures 5, 6) Clock Pulse Frequency (with PE = low) fmax (Figures 4, 5, 6) Clock or Inhibit Rise and Fall Time tr, tf (Figures 5, 6) tsu (Figure 2) Hold Time Preset Enable to Pn Preset Enable Pulse Width th (Figure 3) tw (Figure 4) Reset Pulse Width tw (Figure 8) Reset Removal Time trem (Figure 8) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 - - - - - - - - - - - - - - - 250 100 80 - - - - - - 90 50 40 30 30 30 250 100 80 350 250 200 10 20 30 550 225 160 240 130 100 260 120 100 250 110 80 220 100 80 125 50 40 2.0 5.0 6.6 - - - 40 15 10 - 15 -5 0 125 50 40 175 125 100 - 110 - 30 - 20 1100 450 320 480 260 200 520 240 200 500 220 160 440 200 160 - - - 1.5 3.0 4.0 15 5 4 - - - - - - - - - - - - - - - ns ns ns ns ns MHz ms Setup Time Pn to Preset Enable ns ns ns ns ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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MC14526B
VDD = -VGS CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 0" EXTERNAL POWER SUPPLY IOH VOH VDD = VGS CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 0" EXTERNAL POWER SUPPLY IOL VOL
VSS
VSS
Figure 1. Typical Output Source Characteristics Test Circuit
Figure 2. Typical Output Sink Characteristics Test Circuit
VDD CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 0" VSS PULSE GENERATOR CL CL CL CL CL Q or 0" C L* TEST POINT
DEVICE UNDER TEST
20 ns CLOCK
20 ns VDD 90% 50% 10% VSS VARIABLE 50% DUTY CYCLE WIDTH
*Includes all probe and jig capacitance.
Figure 3. Power Dissipation
Figure 4. Test Circuit
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MC14526B
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10% tw 1/fmax tPLH ANY Q OR 0" 90% 50% 10% tTLH tTHL tPHL ANY Q OR 0" 90% 50% 10% tTLH tTHL tPLH tf VDD INHIBIT VSS tf 90% 50% 10% tw 1/fmax tPHL tr VDD VSS
Figure 5.
Figure 6.
tw VDD RESET tr ANY P 90% 50% 10% tPLH ANY Q 50% tPHL tf VDD VSS ANY Q 50% VSS tPHL 50%
trem CLOCK VDD 50% VSS
Figure 7.
Figure 8.
VALID tr PRESET ENABLE 90% 50% 10% tPHL 0" 50% tPLH tf VDD GND PRESET ENABLE tw ANY P 50% VSS tsu 50% VSS th VDD VDD
Figure 9.
Figure 10.
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MC14526B
MC14526B LOGIC DIAGRAM (Binary Down Counter)
P0 5
Q0 7
P1 11
Q1 9
P2 14
Q2 15
P3 2
Q3 1
DR C T PE Q VDD
D RQ C T PE Q VDD
D RQ C T PE Q
D RQ C T PE Q
CF PE INHIBIT
13 3 4 12 0"
CLOCK RESET
10
6
APPLICATIONS INFORMATION
Divide-By-N, Single Stage Cascaded, Presettable Divide-By-N
Figure 11 shows a single stage divide-by-N application. To initialize counting a number, N is set on the parallel inputs (P0, P1, P2, and P3) and reset is taken high asynchronously. A zero is forced into the master and slave of each bit and, at the same time, the "0" output goes high. Because Preset Enable is tied to the "0" output, preset is enabled. Reset must be released while the Clock is high so the slaves of each bit may receive N before the Clock goes low. When the Clock goes low and Reset is low, the "0" output goes low (if P0 through P3 are unequal to zero). The counter downcounts with each rising edge of the Clock. When the counter reaches the zero state, an output pulse occurs on "0" which presets N. The propagation delays from the Clock's rising and falling edges to the "0" output's rising and falling edges are about equal, making the "0" output pulse approximately equal to that of the Clock pulse. The Inhibit pin may be used to stop pulse counting. When this pin is taken high, decrementing is inhibited.
Figure 12 shows a three stage cascade application. Taking Reset high loads N. Only the first stage's Reset pin (least significant counter) must be taken high to cause the preset for all stages, but all pins could be tied together, as shown. When the first stage's Reset pin goes high, the "0" output is latched in a high state. Reset must be released while Clock is high and time allowed for Preset Enable to load N into all stages before Clock goes low. When Preset Enable is high and Clock is low, time must be allowed for the zero digits to propagate a Cascade Feedback to the first non-zero stage. Worst case is from the most significant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to one (i.e. N = 1). After N is loaded, each stage counts down to zero with each rising edge of Clock. When any stage reaches zero and the leading stages (more significant bits) are zero, the "0" output goes high and feeds back to the preceding stage. When all stages are zero, the Preset Enable automatically loads N while the Clock is high and the cycle is renewed.
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MC14526B
P0 P1 P2 P3 CF RESET INHIBIT CLOCK PE Q0 Q1 Q2 Q3 0"
N VDD VSS
BUFFER
fin
N
fin
Figure 11. / N Counter
LSB N0 N1 N2 N3 P0 P1 P2 P3 CLOCK INHIBIT RESET CF 0" PE VSS Q0 Q1 Q2 Q3
N4 N5 N6 N7 P0 P1 P2 P3 CLOCK INHIBIT RESET CF 0" PE VSS Q0 Q1 Q2 Q3
MSB N8 N9 N10 N11 P0 P1 P2 P3 CLOCK INHIBIT RESET Q0 Q1 Q2 Q3 CF 0" PE VDD
fin VSS VDD
LOAD N
10 KW VSS
BUFFER fin N
Figure 12. 3 Stages Cascaded
ORDERING INFORMATION
Device MC14526BCP MC14526BCPG MC14526BDW MC14526BDWG MC14526BDWR2 MC14526BDWR2G MC14526BF MC14526BFG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) 50 Units / Rail 1000 / Tape & Reel 47 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14526B
PACKAGE DIMENSIONS
PDIP-16 CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16WB CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
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L
MC14526B
PACKAGE DIMENSIONS
SOEIAJ-16 CASE 966-01 ISSUE A
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC14526B/D

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